By Jaakko Harkonen
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This publication constitutes the refereed complaints of the ninth overseas Symposium on useful features of Declarative Languages, PADL 2007, held in great, France, in January 2007, co-located with POPL 2007, the Symposium on rules of Programming Languages. the nineteen revised complete papers offered including invited papers have been conscientiously reviewed and chosen from fifty eight submissions.
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8 Distance (um) Figure 27. Simulated diffusion profiles; a) temperature profile described in previous section b) same temperature profile followed by 14 hours soak at 7000C. Simulations have been carrier out with ICECREM process simulator. According to the simulations, 14 hours heat treatment reduces sheet resistance from 56,7 Ω/sqr to 55,0 Ω/sqr. In multicrystalline silicon, extended defects like grain boundaries and dislocations offer preferred sites for precipitation of metallic impurities. Electrical activity of these defects is known to be strongly dependent on impurities , .
1011cm-3 is the lowest limit of intentionally introduced iron contamination. Therefore, the influence of iron to long lifetimes remains therefore to some extent unclear. 31 Typical µPCD lifetime map of a non –processed mc –Si wafer is shown in Figure 15. This particular wafer has been wire sawed so that the DS process induced crucible contamination is apparent in the right edge of the wafer. Figure 15. µPCD lifetime map of a non –processed Scanwafer mc –Si wafer. Lifetime in the contaminated areas are about 1µs which, according to the graph in Figure 14.
Frequency of the microwave signal is between 10 –11 GHz and it has been adjusted separately for each sample in order to get the highest possible reflected signal from decaying minority carriers. Several thousands of points have been measured in each wafer. A five millimeter wide region has been excluded from each wafer edge in order to eliminate possible measurement errors caused by distorted microwave reflectance. 1 Experimental procedure Two different diffusion programs have been carried out for class A and class B wafers.